简单电阻比较器电路形成鲁棒的Hopfield神经网络ADC

　　Hopfield网络可以将模拟信号转换成数字形式，实现联想记忆、信号估计和组合最优化，类似于人类视网膜实现第一极信号处理的方法。本设计方案探究了Hopfield神经网络ADC的范例。

　　简单的转换器由一层神经元组成，其接收模拟输入，并产生数字位输出；这样的神经元构成了一种自适应和分布性的处理网络。这些神经元由电压比较器组成，驱动模拟转换器或跟随器，从转换器或比较器的模拟输出到跟随器之间连接反馈电阻（图1和图2）。参考和模拟输入电压驱动神经网络，数字输出来源于网络中的比较器。Hopfield网络具有学习能力；本设计方案的电路采用不同的自适应学习规则，通过使用可选的比较器-转换器/比较器-跟随器方案，电导节点规划方案——反馈电阻的倒数——在输入比较器之间，和位顺序读出器。

　　随着模拟输入电压的增加，电路产生单调增加（比较器-转换器方案）或减少（比较器-跟随器方案）位-字输出。减少输出是增加输出的补码，建议使用有负号的位操作。此外，形成转换器到模拟输入电压的数字响应，在不同程度上使用不同的电导节点规划作为

规则适应的一部分。为了更多的适应性，颠倒数字读出器的位顺序考虑模拟输入/数字输出特性的电路响应映射。

　　简单的声明一些符号和含义来构造两个转换器。对能量函数，有抵抗力的网络电导——神经键的权重（S）以倒数电阻的形式(R)——定义S_IJ=1/R_IJ，在此I 为第I 级的输入比较器，J 为第J 级到第I 级比较器的反馈路径，I 不等于J ——也就是说，没有比较器的自反馈路径。第I 级比较器的输入终端和参考电压V_R之间的电导，定义为S_IR=1/R_IR。第I 级比较器的输入终端和模拟输入信号电压V_S的电导，定义为S_IS=1/R_IS。

　　对绘曲线装置，Y为规一化输出位变量，X为非零平均值（小于1）到1的规一化输入模拟电压。A、B和C为用曲线方程Y=1–A×(1–X)^C拟合的常数，补充曲线方程Y=A×(1–X)^C，在此，A为系数，B为X的较低限制，且小于1，C为功率常数。对位格式读出器反转，有曲线方程Y=A×(X–B)^C和补充曲线方程Y=1–A×(X–B)^C。

　　图1显示了一个使用比较器驱动电压转换器的4位神经网络ADC。比较器的正端连接到输入节点，负端接地。这个网络的基础是一半的反转因数——也就是说，两个倒数因数——输入节点的电导SIJ=–1×2^(2–I–J)，在此，–1的参数来自相关电阻的负反馈；S_IR=2^(1–2×I);和S_IS=2^(1–I)。为确定节点电阻，选择最大节点电阻为1000Ω，相应的最小电导为0.0078125，而最小节点电阻7.8125Ω，相应的最大电导为1。按电导和终端之间的比例计算所有电阻。使用这些值，可以构造表1。表中列出了范围从最重要到最次要的位。表格显示的数字化过程不准确，因为其不是线性的，造成输入电压和许多中间位字的丢失。但是过程是精确的，因为其在相当大的输入电压范围内是可重复的。从表格可以得到下面的曲线拟合方程：

Y=1–1.6243×(1–X)^3.1508。当X覆盖归一化的0.1427到1范围，A=1.6243，B=0.1427和C=3.1508。Y方程实际上为三次方，其数量上显示出数字化过程的高度非线性特性。可以获得“错乱”的映射——也就是说，不是一个真正的反映，或假的——从电路通过反转位顺序读出器，归一化图形上直线曲线的版本，所以曲线方程结果为：Y=1.6243×(X–0.1427)^3.1508。

　　没有模拟输入电压转换，例如使用查询表格或对数放大器处理输入电压，或数字校准逻辑，简单Hopfield神经网络转换器的数字响应为非线性和粗略。然而，由于输出精度的鲁棒性，这些响应仍可能对结合存储器和模式分类的应用有效。

　　确实，由于输出数字的稳定性，Hopfield神经转换器引入了不需要的模拟输入信号噪声或变化。这个情形与传统模拟传输媒介和数字计算装置之间的接口电路形成了强烈的对比。本设计方案显示了灵活的电路适应性从神经网络ADC产生各种形式的稳定数字输出，取决于神经网络信号处理的设计人员需求。这种适应性有各种输入节点电导规划的形式；比较器/转换器和比较器/跟随器结合；位读出器的可选顺序类型源于比较器。

　　英文原文：

　　Flexible Hopfield neural-network ADCs quash noise

　　Simple resistor-comparator circuits form a robust Hopfield neural-network ADC.

　　Paul J Rose, PhD, Mental Automation, Renton, WA; Editedby Charles H Small and Fran Granville -- EDN, 1/24/2008

　　A Hopfield network can convert analog signals into digital format and can perform associative recalling, signal estimation, and combinatorial optimization similar to the way a human retina performs first-level signal processing. This Design Idea explores the Hopfield-neural-network paradigm for ADCs.

　　Simple converters comprise one-layer neurons that accept analog inputs and generate digital-bit outputs; such neurons make up one form of adaptive- and distributive-processing networks. These neurons comprise voltage comparators driving either analog inverters or followers and fully connected feedback resistors from the analog outputs of the inverters or followers to the comparators (figure 1 and figure 2). Reference and analog-input voltages drive the neural networks, and digital outputs come from the comparators in the networks. Hopfield networks have learning capabilities; the circuit in this Design Idea can apply different adaptive-learning rules by using alternative comparator-inverter/comparator-follower schemes, conductance-node-layout schemes—reciprocals of the feedback resistances—between the input comparators, and bit-order readouts.

　　As the analog-input voltage increases, the circuit can produce either monotonically increasing (from a comparator-inverter scheme) or decreasing (from a comparator-follower scheme) bit-word outputs. Decreasing outputs are the complements of increasing outputs and suggest subtractive-bit operations. Further, you can shape the digital responses of the converters to analog-input voltages in varying degrees using different conductance-node layouts as part of rule adaptation. For further flexibility, reversing bit order for digital readouts allows for reflection of circuit responses about analog-input/digital-output characteristics.

　　You can simply state a few symbols and their meanings to construct the two converters. For energy functions, the resistive network conductances—synapse weightings (S) in the form of reciprocal resistances (R)—have the designations SIJ="1/RIJ", where I is the Ith input comparator, J is the Jth feedback path to the Ith comparator, and I does not equal J—that is, there is no self-feedback path of the comparator to itself. The conductance between the input terminal of the Ith comparator and the reference voltage, VR, has the designation SIR="1/RIR". The conductance between the input terminal of the Ith comparator and the analog-input-signal voltage, VS, has the designation SIS="1/RIS".

　　For graphical curve fittings, Y is the normalized output-bit variable, and X is the normalized input analog voltage from a nonzero average value (less than one) to one. A, B, and C are curve-fitting constants in the curve equation Y="1"–A×(1–X)C and the complementary-curve equation Y="A"×(1–X)C, where A is a coefficient, B is the lower limit for X and is less than one, and C is a power constant. For bit-pattern readout reversals, you can have the curve equation Y="A"×(X–B)C and the complementary-curve equation Y="1"–A×(X–B)C.

　　Figure 1 shows a 4-bit neural ADC employing voltage inverters that comparators feed. The comparators connect with their positive terminals joined to input nodes and with their negative terminals grounded. The bases of this network are inverse factors of one-half—that is, reciprocal factors of two—input-node conductances SIJ=–1×2(2–I–J), where the –1 factor comes from negative feedback through the related resistor; SIR="2"(1–2×I); and SIS="2"(1–I). To determine node resistances, choose a maximum node resistance of 1000Ω corresponding to a minimum conductance of 0.0078125, and a minimum node resistance of 7.8125Ω corresponding to a maximum conductance of one. Calculate all other resistances from the ratios between the extremes of conductances. Using these values, you can construct Table 1. The table lists bits ranging from the most significant bit to the least significant. The table shows that the digitization process is inaccurate in that it is not linear with input voltage and with many intermediate bit words missing. But the process is precise because it is repeatable over sizable input-voltage ranges. From the table, you can derive the following curve-fitting equation: Y="1"–1.6243×(1–X)3.1508. When X is over the normalized range of 0.1427 to 1, A="1".6243, B="0".1427, and C="3".1508. The Y equation is essentially cubic, and it quantitatively shows the highly nonlinear nature of the

digitization process. You can obtain a “flipped” mirror—that is, not a true mirror, or pseudoscopic—version of the curve of the straight line on a normalized graph by reversing the bit-order readout from the circuit so that the resulting curve equation would be: Y="1".6243×(X–0.1427)3.1508.

　　Without analog-input-voltage transformation, such as the use of look-up tables or logarithmic amplifiers to process the input voltage, or digital corrective logic, digital responses from simple Hopfield neural converters are nonlinear and crude. However, these responses are still possibly useful for such applications as associative memory and pattern classification because of robustness in output precision.

　　Indeed, because of output digital stability, the Hopfield neural converter can allow for unwanted analog-input-signal noisiness or variations. This scenario is in strong contrast to conventional interface circuits between analog-transmission media and digital-computing machines. This Design Idea shows that flexible circuit adaptability can exist in producing various forms of stable digital outputs from neural ADCs depending on a designer’s needs for neural-network-signal processing. This adaptability can be in the forms of various input-node-conductance layouts; comparator/inverter and comparator/follower combinations; and the selected order of bit-readout patterns from the comparators.

　　英文原文地址：http://www.edn.com/article/CA6518681.html

作者：EDN | Paul J Rose, PhD, Mental Automation, Renton, WA